The number of memory blocks in a semiconductor device in an embedded system are limited and each of these memory blocks have fixed size. Due to this constraint, only some limited combinations of width and depth configurations for target design memory blocks can be implemented to the memory blocks in the embedded system. The implementation is typically performed automatically by using Electronic Design Automation (EDA) tools.
Conventional EDA tools can directly map a target design memory to an embedded memory block automatically with one-to-one correspondence. These conventional tools may be able to implement multiple small target design memory blocks to a single embedded memory block only when the combined width of the multiple small target design memory blocks is less than or equal to the width of the single embedded memory block. However, the conventional EDA tools are oblivious to the multiple small target design memory blocks being overlapping or non-overlapping.
These shortcomings in the conventional EDA tools require larger number of embedded memory blocks in a semiconductor device. This further leads to necessity of more expensive semiconductor devices that have more number of memory blocks. Moreover, usage of more number of memory blocks may lead to routing congestion and reduced timing performance and may thus demand larger size of the semiconductor device and more power consumption.